/* Copyright 2020 UPMEM. All rights reserved.
 * Use of this source code is governed by a BSD-style license that can be
 * found in the LICENSE file.
 */

#include <stddef.h>
#include <dpu_description.h>

static struct _dpu_description_t vD_description = {
    .hw.signature.chip_id = vD,
    .hw.topology.nr_of_control_interfaces = 8,
    .hw.topology.nr_of_dpus_per_control_interface = 8,
    .hw.timings.carousel.cmd_duration = 2,
    .hw.timings.carousel.cmd_sampling = 1,
    .hw.timings.carousel.res_duration = 2,
    .hw.timings.carousel.res_sampling = 1,
    .hw.timings.reset_wait_duration = 20,
    .hw.timings.std_temperature = 110,
    .hw.timings.fck_frequency_in_mhz = 1000,
    .hw.timings.clock_division = 2,
    .hw.memories.mram_size = 67108864,
    .hw.memories.wram_size = 16384,
    .hw.memories.iram_size = 4096,
    .hw.dpu.nr_of_threads = 24,
    .hw.dpu.nr_of_atomic_bits = 256,
    .hw.dpu.nr_of_notify_bits = 40,
    .hw.dpu.nr_of_work_registers_per_thread = 24,
};

static struct _dpu_description_t vD_cas_description = {
    .hw.signature.chip_id = vD_cas,
    .hw.topology.nr_of_control_interfaces = 1,
    .hw.topology.nr_of_dpus_per_control_interface = 1,
    .hw.timings.carousel.cmd_duration = 2,
    .hw.timings.carousel.cmd_sampling = 1,
    .hw.timings.carousel.res_duration = 2,
    .hw.timings.carousel.res_sampling = 1,
    .hw.timings.reset_wait_duration = 20,
    .hw.timings.std_temperature = 110,
    .hw.timings.fck_frequency_in_mhz = 1000,
    .hw.timings.clock_division = 2,
    .hw.memories.mram_size = 67108864,
    .hw.memories.wram_size = 16384,
    .hw.memories.iram_size = 4096,
    .hw.dpu.nr_of_threads = 24,
    .hw.dpu.nr_of_atomic_bits = 256,
    .hw.dpu.nr_of_notify_bits = 40,
    .hw.dpu.nr_of_work_registers_per_thread = 24,
};

static struct _dpu_description_t vD_fun_description = {
    .hw.signature.chip_id = vD_fun,
    .hw.topology.nr_of_control_interfaces = 1,
    .hw.topology.nr_of_dpus_per_control_interface = 1,
    .hw.timings.carousel.cmd_duration = 2,
    .hw.timings.carousel.cmd_sampling = 1,
    .hw.timings.carousel.res_duration = 2,
    .hw.timings.carousel.res_sampling = 1,
    .hw.timings.reset_wait_duration = 20,
    .hw.timings.std_temperature = 110,
    .hw.timings.fck_frequency_in_mhz = 1000,
    .hw.timings.clock_division = 2,
    .hw.memories.mram_size = 67108864,
    .hw.memories.wram_size = 16384,
    .hw.memories.iram_size = 4096,
    .hw.dpu.nr_of_threads = 24,
    .hw.dpu.nr_of_atomic_bits = 256,
    .hw.dpu.nr_of_notify_bits = 40,
    .hw.dpu.nr_of_work_registers_per_thread = 24,
};

static struct _dpu_description_t vD_asic1_description = {
    .hw.signature.chip_id = vD_asic1,
    .hw.topology.nr_of_control_interfaces = 1,
    .hw.topology.nr_of_dpus_per_control_interface = 1,
    .hw.timings.carousel.cmd_duration = 2,
    .hw.timings.carousel.cmd_sampling = 1,
    .hw.timings.carousel.res_duration = 2,
    .hw.timings.carousel.res_sampling = 1,
    .hw.timings.reset_wait_duration = 20,
    .hw.timings.std_temperature = 110,
    .hw.timings.fck_frequency_in_mhz = 1000,
    .hw.timings.clock_division = 2,
    .hw.memories.mram_size = 67108864,
    .hw.memories.wram_size = 16384,
    .hw.memories.iram_size = 4096,
    .hw.dpu.nr_of_threads = 24,
    .hw.dpu.nr_of_atomic_bits = 256,
    .hw.dpu.nr_of_notify_bits = 40,
    .hw.dpu.nr_of_work_registers_per_thread = 24,
};

static struct _dpu_description_t vD_asic8_description = {
    .hw.signature.chip_id = vD_asic8,
    .hw.topology.nr_of_control_interfaces = 1,
    .hw.topology.nr_of_dpus_per_control_interface = 8,
    .hw.timings.carousel.cmd_duration = 6,
    .hw.timings.carousel.cmd_sampling = 3,
    .hw.timings.carousel.res_duration = 6,
    .hw.timings.carousel.res_sampling = 3,
    .hw.timings.reset_wait_duration = 20,
    .hw.timings.std_temperature = 110,
    .hw.timings.fck_frequency_in_mhz = 1000,
    .hw.timings.clock_division = 2,
    .hw.memories.mram_size = 67108864,
    .hw.memories.wram_size = 16384,
    .hw.memories.iram_size = 4096,
    .hw.dpu.nr_of_threads = 24,
    .hw.dpu.nr_of_atomic_bits = 256,
    .hw.dpu.nr_of_notify_bits = 40,
    .hw.dpu.nr_of_work_registers_per_thread = 24,
};

static struct _dpu_description_t vD_fpga1_description = {
    .hw.signature.chip_id = vD_fpga1,
    .hw.topology.nr_of_control_interfaces = 1,
    .hw.topology.nr_of_dpus_per_control_interface = 1,
    .hw.timings.carousel.cmd_duration = 2,
    .hw.timings.carousel.cmd_sampling = 1,
    .hw.timings.carousel.res_duration = 2,
    .hw.timings.carousel.res_sampling = 1,
    .hw.timings.reset_wait_duration = 20,
    .hw.timings.std_temperature = 110,
    .hw.timings.fck_frequency_in_mhz = 1000,
    .hw.timings.clock_division = 2,
    .hw.memories.mram_size = 67108864,
    .hw.memories.wram_size = 16384,
    .hw.memories.iram_size = 4096,
    .hw.dpu.nr_of_threads = 24,
    .hw.dpu.nr_of_atomic_bits = 256,
    .hw.dpu.nr_of_notify_bits = 40,
    .hw.dpu.nr_of_work_registers_per_thread = 24,
};

static struct _dpu_description_t vD_fpga8_description = {
    .hw.signature.chip_id = vD_fpga8,
    .hw.topology.nr_of_control_interfaces = 1,
    .hw.topology.nr_of_dpus_per_control_interface = 8,
    .hw.timings.carousel.cmd_duration = 2,
    .hw.timings.carousel.cmd_sampling = 1,
    .hw.timings.carousel.res_duration = 2,
    .hw.timings.carousel.res_sampling = 1,
    .hw.timings.reset_wait_duration = 20,
    .hw.timings.std_temperature = 110,
    .hw.timings.fck_frequency_in_mhz = 1000,
    .hw.timings.clock_division = 2,
    .hw.memories.mram_size = 67108864,
    .hw.memories.wram_size = 16384,
    .hw.memories.iram_size = 4096,
    .hw.dpu.nr_of_threads = 24,
    .hw.dpu.nr_of_atomic_bits = 256,
    .hw.dpu.nr_of_notify_bits = 40,
    .hw.dpu.nr_of_work_registers_per_thread = 24,
};

static struct _dpu_description_t vD_asic4_description = {
    .hw.signature.chip_id = vD_asic4,
    .hw.topology.nr_of_control_interfaces = 1,
    .hw.topology.nr_of_dpus_per_control_interface = 4,
    .hw.timings.carousel.cmd_duration = 2,
    .hw.timings.carousel.cmd_sampling = 1,
    .hw.timings.carousel.res_duration = 2,
    .hw.timings.carousel.res_sampling = 1,
    .hw.timings.reset_wait_duration = 20,
    .hw.timings.std_temperature = 110,
    .hw.timings.fck_frequency_in_mhz = 1000,
    .hw.timings.clock_division = 2,
    .hw.memories.mram_size = 67108864,
    .hw.memories.wram_size = 16384,
    .hw.memories.iram_size = 4096,
    .hw.dpu.nr_of_threads = 24,
    .hw.dpu.nr_of_atomic_bits = 256,
    .hw.dpu.nr_of_notify_bits = 40,
    .hw.dpu.nr_of_work_registers_per_thread = 24,
};

static struct _dpu_description_t vD_fpga4_description = {
    .hw.signature.chip_id = vD_fpga4,
    .hw.topology.nr_of_control_interfaces = 1,
    .hw.topology.nr_of_dpus_per_control_interface = 4,
    .hw.timings.carousel.cmd_duration = 2,
    .hw.timings.carousel.cmd_sampling = 1,
    .hw.timings.carousel.res_duration = 2,
    .hw.timings.carousel.res_sampling = 1,
    .hw.timings.reset_wait_duration = 20,
    .hw.timings.std_temperature = 110,
    .hw.timings.fck_frequency_in_mhz = 1000,
    .hw.timings.clock_division = 2,
    .hw.memories.mram_size = 67108864,
    .hw.memories.wram_size = 16384,
    .hw.memories.iram_size = 4096,
    .hw.dpu.nr_of_threads = 24,
    .hw.dpu.nr_of_atomic_bits = 256,
    .hw.dpu.nr_of_notify_bits = 40,
    .hw.dpu.nr_of_work_registers_per_thread = 24,
};

static struct _dpu_description_t vD_asic1_v1_4_description = {
    .hw.signature.chip_id = vD_asic1_v1_4,
    .hw.topology.nr_of_control_interfaces = 1,
    .hw.topology.nr_of_dpus_per_control_interface = 1,
    .hw.timings.carousel.cmd_duration = 2,
    .hw.timings.carousel.cmd_sampling = 1,
    .hw.timings.carousel.res_duration = 2,
    .hw.timings.carousel.res_sampling = 1,
    .hw.timings.reset_wait_duration = 20,
    .hw.timings.std_temperature = 110,
    .hw.timings.fck_frequency_in_mhz = 1000,
    .hw.timings.clock_division = 2,
    .hw.memories.mram_size = 67108864,
    .hw.memories.wram_size = 16384,
    .hw.memories.iram_size = 4096,
    .hw.dpu.nr_of_threads = 16,
    .hw.dpu.nr_of_atomic_bits = 64,
    .hw.dpu.nr_of_notify_bits = 0,
    .hw.dpu.nr_of_work_registers_per_thread = 24,
};

static struct _dpu_description_t vD_asic8_v1_4_description = {
    .hw.signature.chip_id = vD_asic8_v1_4,
    .hw.topology.nr_of_control_interfaces = 1,
    .hw.topology.nr_of_dpus_per_control_interface = 8,
    .hw.timings.carousel.cmd_duration = 6,
    .hw.timings.carousel.cmd_sampling = 3,
    .hw.timings.carousel.res_duration = 6,
    .hw.timings.carousel.res_sampling = 3,
    .hw.timings.reset_wait_duration = 20,
    .hw.timings.std_temperature = 110,
    .hw.timings.fck_frequency_in_mhz = 1000,
    .hw.timings.clock_division = 2,
    .hw.memories.mram_size = 67108864,
    .hw.memories.wram_size = 16384,
    .hw.memories.iram_size = 4096,
    .hw.dpu.nr_of_threads = 16,
    .hw.dpu.nr_of_atomic_bits = 64,
    .hw.dpu.nr_of_notify_bits = 0,
    .hw.dpu.nr_of_work_registers_per_thread = 24,
};

static struct _dpu_description_t vD_fpga1_v1_4_description = {
    .hw.signature.chip_id = vD_fpga1_v1_4,
    .hw.topology.nr_of_control_interfaces = 1,
    .hw.topology.nr_of_dpus_per_control_interface = 1,
    .hw.timings.carousel.cmd_duration = 2,
    .hw.timings.carousel.cmd_sampling = 1,
    .hw.timings.carousel.res_duration = 2,
    .hw.timings.carousel.res_sampling = 1,
    .hw.timings.reset_wait_duration = 20,
    .hw.timings.std_temperature = 110,
    .hw.timings.fck_frequency_in_mhz = 1000,
    .hw.timings.clock_division = 2,
    .hw.memories.mram_size = 67108864,
    .hw.memories.wram_size = 16384,
    .hw.memories.iram_size = 4096,
    .hw.dpu.nr_of_threads = 16,
    .hw.dpu.nr_of_atomic_bits = 64,
    .hw.dpu.nr_of_notify_bits = 0,
    .hw.dpu.nr_of_work_registers_per_thread = 24,
};

static struct _dpu_description_t vD_fpga8_v1_4_description = {
    .hw.signature.chip_id = vD_fpga8_v1_4,
    .hw.topology.nr_of_control_interfaces = 1,
    .hw.topology.nr_of_dpus_per_control_interface = 8,
    .hw.timings.carousel.cmd_duration = 2,
    .hw.timings.carousel.cmd_sampling = 1,
    .hw.timings.carousel.res_duration = 2,
    .hw.timings.carousel.res_sampling = 1,
    .hw.timings.reset_wait_duration = 20,
    .hw.timings.std_temperature = 110,
    .hw.timings.fck_frequency_in_mhz = 1000,
    .hw.timings.clock_division = 2,
    .hw.memories.mram_size = 67108864,
    .hw.memories.wram_size = 16384,
    .hw.memories.iram_size = 4096,
    .hw.dpu.nr_of_threads = 16,
    .hw.dpu.nr_of_atomic_bits = 64,
    .hw.dpu.nr_of_notify_bits = 0,
    .hw.dpu.nr_of_work_registers_per_thread = 24,
};

static struct _dpu_description_t vD_asic4_v1_4_description = {
    .hw.signature.chip_id = vD_asic4_v1_4,
    .hw.topology.nr_of_control_interfaces = 1,
    .hw.topology.nr_of_dpus_per_control_interface = 4,
    .hw.timings.carousel.cmd_duration = 2,
    .hw.timings.carousel.cmd_sampling = 1,
    .hw.timings.carousel.res_duration = 2,
    .hw.timings.carousel.res_sampling = 1,
    .hw.timings.reset_wait_duration = 20,
    .hw.timings.std_temperature = 110,
    .hw.timings.fck_frequency_in_mhz = 1000,
    .hw.timings.clock_division = 2,
    .hw.memories.mram_size = 67108864,
    .hw.memories.wram_size = 16384,
    .hw.memories.iram_size = 4096,
    .hw.dpu.nr_of_threads = 16,
    .hw.dpu.nr_of_atomic_bits = 64,
    .hw.dpu.nr_of_notify_bits = 0,
    .hw.dpu.nr_of_work_registers_per_thread = 24,
};

static struct _dpu_description_t vD_fpga4_v1_4_description = {
    .hw.signature.chip_id = vD_fpga4_v1_4,
    .hw.topology.nr_of_control_interfaces = 1,
    .hw.topology.nr_of_dpus_per_control_interface = 4,
    .hw.timings.carousel.cmd_duration = 2,
    .hw.timings.carousel.cmd_sampling = 1,
    .hw.timings.carousel.res_duration = 2,
    .hw.timings.carousel.res_sampling = 1,
    .hw.timings.reset_wait_duration = 20,
    .hw.timings.std_temperature = 110,
    .hw.timings.fck_frequency_in_mhz = 1000,
    .hw.timings.clock_division = 2,
    .hw.memories.mram_size = 67108864,
    .hw.memories.wram_size = 16384,
    .hw.memories.iram_size = 4096,
    .hw.dpu.nr_of_threads = 16,
    .hw.dpu.nr_of_atomic_bits = 64,
    .hw.dpu.nr_of_notify_bits = 0,
    .hw.dpu.nr_of_work_registers_per_thread = 24,
};

const dpu_description_t dpu_chip_descriptions[NEXT_DPU_CHIP_IDX] = {
    [0] = &vD_description,
    [1] = &vD_cas_description,
    [2] = &vD_fun_description,
    [3] = &vD_asic1_description,
    [4] = &vD_asic8_description,
    [5] = &vD_fpga1_description,
    [6] = &vD_fpga8_description,
    [7] = &vD_asic4_description,
    [8] = &vD_fpga4_description,
    [9] = &vD_asic1_v1_4_description,
    [10] = &vD_asic8_v1_4_description,
    [11] = &vD_fpga1_v1_4_description,
    [12] = &vD_fpga8_v1_4_description,
    [13] = &vD_asic4_v1_4_description,
    [14] = &vD_fpga4_v1_4_description,
};
